Broadcom Wi-Fi chips, and Apple smartphones, tablets and computers held responsible for patent infringements
| March 18, 2022
California Institute of Technology v. Broadcom Ltd.
Decided on February 4, 2022
Lourie, Linn (Senior), and Dyk. Court opinion by Linn. Concurring-in-part-and-dissenting-in-part Opinion by Dyk.
Summary
On appeals from the district court for the judgment of infringement of patents in favor of Caltech, the patentee, against Broadcom totaling $288,246,156, and against Apple totaling $885,441,828 and denial of JMOL on infringement thereof, the Federal Circuit affirmed the district court’s denial of the JMOL because the Court was not persuaded that the district court erred in construing the term “repeat” in the claim of the patent in issue, and that the record before the jury permits only a verdict of no infringement. Judge Dyk filed a dissenting opinion regarding the denial of JMOL on infringement.
Details
I. Background
The California Institute of Technology (“Caltech”) filed an infringement suit against Broadcom Limited, Broadcom Corporation, and Avago Technologies Ltd. (collectively “Broadcom”) and Apple Inc. (“Apple”) at the District Court for the Central District of California (“the district court”). Caltech alleged infringement of its U.S. Patents No. 7,116,710 (“the ’710 patent”), No. 7,421,032 (“the ’032 patent”), and No. 7,916,781 (“the ’781 patent”) by certain Broadcom Wi- Fi chips and Apple products incorporating those chips, including smartphones, tablets, and computers. The accused Broadcom chips were developed and supplied to Apple pursuant to Master Development and Supply Agreements negotiated and entered into in the United States.
While the case involves several issues regarding these patents, this case review focuses on the issue of claim construction regarding the term “repeat” in the ’710 patent.
Caltech argued that the accused chips infringed claims 20 and 22 of the ’710 patent. Claims 20 and 22 of the ’710 patent depend from claim 15, which provides:
15. A coder comprising: a first coder having an input configured to receive a stream of bits, said first coder operative to repeat said stream of bits irregularly and scramble the repeated bits; and a second coder operative to further encode bits output from the first coder at a rate within 10% of one. (emphasis added)
Caltech specifically identified as infringing products two encoders contained in the Broadcom chips- a Richardson-Urbanke (“RU”) encoder and a low-area (“LA”) encoder. In the accused encoders, incoming information bits are provided to AND gates in the RU encoder or multiplexers in the LA encoder.
In its brief , Broadcom presents the following table, using the example of the functioning of a single AND gate, to show how outputs are determined by the two inputs:
| Input 1 (Information Bit) | Input 2 (Parity-Check Bit) | AND Gate Output |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
For each AND gate, the output of the gate is 1 if both inputs (the information bit and the parity-check bit) are l ; otherwise, the output is 0. One consequence of this logic is that if the parity-check bit is 1 (as shown in rows two and four), then the output is identical to the information-bit input. If the parity-check bit is 0, the output is 0, 1regardless of the value of the input (rows one and three).
For the claim construction regarding the term “repeat” in the ’710 patent, Caltech advocated for the term’s plain and ordinary meaning. In contrast, Apple and Broadcom proposed a narrower construction, contending that “repeat” should be construed as “creating a new bit that corresponds to the value of an original bit (i.e., a new copy) by storing the new copied bit in memory. A reuse of a bit is not a repeat of a bit.” (emphasis added)
In pre-trial, at the conclusion of the Markman hearing, the district court construed the term “repeat” to have its plain and ordinary meaning and noted that the repeated bits “are a construct distinct from the original bits from which they are created,” but that they need not be generated by storing new copied bits in memory.
During trial, the district court instructed the jury that the term “repeat” means “generation of additional bits, where generation can include, for example, duplication or reuse of bits.” (emphasis added) Apple and Broadcom then argued that the chips did not infringe the ’710 patent because they did not repeat information bits at all, much less irregularly. The jury ultimately found infringement of all the asserted claims. Broadcom and Apple filed post-trial motions for JMOL and a new trial, challenging the jury’s infringement verdict. The district court denied JMOL, finding no error in its claim construction ruling and concluding that the verdict was supported by substantial evidence.
The district court entered judgment against Broadcom totaling $288,246,156, and against Apple totaling $885,441,828. These awards included pre-judgment interest, as well as post-judgment interest and an ongoing royalty at the rate set by the jury’s verdict.
Broadcom and Apple appealed.
II. The Federal Circuit
The Federal Circuit (“the Court”) affirmed the district court’s construction of the term “repeat” and JMOL on Infringement.
1. Claim Construction of “repeat”
Broadcom and Apple argued that the district court erroneously construed the term “repeat,” contending that the accused AND gates and multiplexers do not “repeat” information bits in the manner claimed, but instead combine the information bits with bits from a parity-check matrix to output new bits reflecting that combination. Broadcom and Apple further argue that the AND gates and multiplexers also do not generate bits “irregularly,” asserting that they output the same number of bits for every information bit.
The Court was not persuaded. The Court stated that the district court correctly observed that the claims require repeating but do not specify how the repeating is to occur: “The claims simply require bits to be repeated, without limiting how specifically the duplicate bits are created or stored in the memory.” (emphasis added) The Court further stated that the specifications confirm that construction and describe two embodiments, neither of which require duplication of bits.
2. JMOL on Infringement
Broadcom and Apple argued that, looking at each gate alone and the “repeat” requirement, AND gate does not “repeat” the inputted information bit “because the AND gate’s output depends on not only the information bit but also the parity-check-matrix bit.”
In contrast, Caltech argued that, considering the system as a whole, each information bit is in fact repeated, and they are not all repeated the same number of times. To support Caltech’s position, Caltech’s expert, Dr. Matthew Shoemake explained that in the parity-check-bit-equals-1 situation (second and fourth rows of the table), the output bit is a “repeat” of the information- bit input. Where the parity-check bit is 1, the gate affirmatively enables the information bit to be duplicated as the output bit. That is a ‘repeat’ … because the information bit in that situation ‘flows through’ to appear again in the output.”
The Court sided Caltech, and affirmed the district court’s denial of JMOL.
III. Concurring-in-part-and-dissenting-in-part Opinion
Judge Dyk disagreed with the majority’s holding that substantial evidence supports the jury’s verdict of infringement of the asserted claims of the ’710 patent (and the ’032 patent) and stated that he would reverse the district court’s denial of JMOL of no literal infringement.
Given that the district court constructed the term “repeat” to mean “generation of additional bits, where generation can include, for example, duplication or reuse of bits,” Judge Dyk located the critical question to be whether there is substantial evidence that the accused devices cause “generation of additional bits.” Judge Dyk then pointed out that the problem for Caltech (and for the majority) is that Caltech never established that the accused devices generate “additional bits,” as required by the district court’s claim construction.
The infringement theory presented at trial explained that the accused devices work as follows: information bits are input into the accused devices, those bits travel down branched wires to the inputs of 972 AND gates, and three to twelve of those AND gates will be open for each information bit, thus outputting the bits a different number of times. In Judge Dyk’s view, for this theory to satisfy Caltech’s burden, Caltech was required to establish where, when, and how additional bits were generated. Judge Dyk stated the record does not support a theory that the branched wires generate additional bits.
Means-Plus-Function: The Achilles’ Heel
| May 9, 2012
Noah Systems, Inc. v. Intuit, Inc.
April 9, 2012
Panel: Rader, O’Malley and Reyna. Opinion by Judge O’Malley
Summary
This decision illustrates that a patent could become invalidated even after surviving challenges of reexamination, which strengthen the presumption of validity, when a challenger discovers the Achilles’ Heel of a means-plus-function claim element resulting in a summary judgment of invalidity by the CAFC. Noah appeals the granting, by the United States District Court for the Western District of Pennsylvania (DC), of Intuit’s Motion for Summary Judgment of Invalidity of USP 5,875,435 (the ‘435 patent) based on indefiniteness for a means-plus-function claim element without the DC hearing evidence of how one of skill in the art would view the specification. The CAFC affirms by finding that the specification discloses no algorithm when the specification discloses an algorithm that only accomplishes one of two identifiable functions performed by the means-plus-function limitation.
