CAFC splits the difference between VLSI and Intel on Claim Construction
| December 28, 2022
VLSI Technology LLC v. Intel Corp.
Decided: November 15, 2022
CHEN, BRYSON, and HUGHES. Opinion by Bryson
Summary:
The Court affirmed the PTAB’s claim construction which had narrowed an interpretation taken from the related District Court’s construction and remanded on a separate claim construction for reading a “used for” aspect out of the claim.
Background:
Intel filed three IPR’s against VLSI’s U.S. Patent No. 7,247,552 (“the ’552 patent”). The ’552 patent is directed to the structures of an integrated circuit that reduce the potential for damage to the interconnect layers and dielectric material when the chip is attached to another electronic component. The two representative claims were claim 1 directed to a device and claim 20 directed to a method. The terms subject to construction are emphasized below.
1. An integrated circuit, comprising:
a substrate having active circuitry;
a bond pad over the substrate;
a force region at least under the bond pad characterized by being susceptible to defects due to stress applied to the bond pad;
a stack of interconnect layers, wherein each interconnect layer has a portion in the force region; and
a plurality of interlayer dielectrics separating the interconnect layers of the stack of interconnect layers and having at least one via for interconnecting two of the interconnect layers of the stack of interconnect layers;
wherein at least one interconnect layer of the stack of interconnect layers comprises a functional metal line underlying the bond pad that is not electrically connected to the bond pad and is used for wiring or interconnect to the active circuitry, the at least one interconnect layer of the stack of interconnect layers further comprising dummy metal lines in the portion that is in the force region to obtain a predetermined metal density in the portion that is in the force region.
20. A method of making an integrated circuit having a plurality of bond pads, comprising:
developing a circuit design of the integrated circuit;
developing a layout of the integrated circuit according to the circuit design, wherein the layout comprises a plurality of metal-containing interconnect layers that extend under a first bond pad of the plurality of bond pads, at least a portion of the plurality of metal-containing interconnect layers underlying the first bond pad and not electrically connected to the bond pad as a result of being used for electrical interconnection not directly connected to the bond pad;
modifying the layout by adding dummy metal lines to the plurality of metal-containing interconnect layers to achieve a metal density of at least forty percent for each of the plurality of metal-containing interconnect layers; and
forming the integrated circuit comprising the dummy metal lines.
VLSI had brought suit in the District of Delaware, charging Intel with infringing the ’552 patent. The District court construed the term “force region,” referencing the specification of the ’552 patent to mean a “region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed.” In the IPRs Intel proposed a construction of “force region” that was consistent with that adopted by the district court and VLSI did not oppose Intel’s proposed construction before the Board.
However, in the course of the IPR proceedings it became apparent that they disagreed as to the meaning of the term “die attach” as set forth in the District court construction.
Intel argued that the term “die attach” refers to any method of attaching the chip to another electronic component, and that the term “die attach” therefore includes attachment by a method known as wire bonding. VLSI argued that the term “die attach” refers to a method of attachment known as “flip chip” bonding, and does not include wire bonding.
The construction was paramount to claim 1 as applying its proposed restrictive definition of “die attach,” VLSI distinguished Intel’s principal prior art reference for the “force region” limitation, U.S. Patent Publication No. 2004/0150112 (“Oda”). Oda discloses attaching a chip to another component using wire bonding but not the flip chip process.
The Board sided with Intel that wire bonding is a type of die attach, and that Oda therefore disclosed a “force region”. Specifically, the Board found that the ’552 patent specification made clear in several places that the term “force region” was not limited to flip chip bonding, but could include wire bonding as well. Based on that finding, the Board concluded that Oda disclosed the “force region” element of claim 1 and was unpatentable for obviousness.
Regarding claim 20 of the ’552 patent, the parties disagreed over the construction of the limitation providing that the “metal-containing interconnect layers” are “used for electrical interconnection not directly connected to the bond pad.” VLSI argued that the phrase requires a connection to active circuitry or the capability to carry electricity. Intel argued that the claim does not require that the interconnection actually carry electricity.
The Board again sided with Intel, asserting the principally relied upon U.S. Patent No. 7,102,223 (“Kanaoka”) teaches the “used for electrical interconnection” limitation. The Board cited to figure 45 of Kanaoka for its disclosure of a die that has a series of interconnect layers, some of which are connected to each other.
VLSI appealed.
CAFC Decision:
VLSI argued that the Board erred in its treatment of the “force region” limitation in claim 1 and in construing the phrase “used for electrical interconnection” in claim 20 to encompass a metallic structure that is not connected to active circuitry.
Claim 1
Regarding the “force region” limitation, VLSI argued that the Board failed to acknowledge and give appropriate weight to the district court’s claim construction. In particular, VLSI based its argument principally on the requirement that the Board “consider” prior claim construction determinations by a district court and give such prior constructions appropriate weight.
However, the CAFC found that the Board was clearly well aware of the district court’s construction, as it was the subject of repeated and extensive discussion in the briefing and in the oral hearing before the PTAB. Further, the Court found that the Board did not reject the district court’s construction, but rather the district court’s construction concealed a fundamental disagreement between the parties as to the proper construction of “force region.”
They held that although the district court defined the term “force region” with reference to “die attach” processes, the district court did not decide— and was not asked to decide—whether the term “die attach,” as used in the patent, included wire bonding or was limited to flip chip bonding. Thus, the CAFC found that the Board addressed an argument not made to the district court, and it reached a conclusion not at odds with the conclusion reached by the district court.
In reaching their decision, the Court noted that other language in the specification of the ‘552 patent indicates that the claimed “force region” is not limited to attachment processes that use flip chip bonding. Restating precedence that claims should not be limited “to preferred embodiments or specific examples in the specification,” they emphasized that even if the term “die attach,” was used in one section of the specification to refer to flip chip bonding in particular other portions of the specification did make clear that the invention was not intended to be limited to flip chip bonding.
VLSI further contended that defining “force region” to mean a region at least directly under the bond pad is legally flawed because the definition restates a requirement that is already in the claims. The Court noted that although caselaw has emphasized redundant construction should not be used, in this case intrinsic evidence makes it clear that the “redundant” construction is correct. Specifically, they stated that the “force region” limitation is best understood as containing a definition of the force region, (“… just as would be the case if the language of the limitation had read ‘a region, referred to as a force region, at least under the bond pad . . .’ or ‘a force region, i.e., a region at least under the bond pad . . . .’), and concluded that the language “is best viewed not as redundant, but merely as clumsily drafted.”
Additionally, VLSI argued the Board was bound by the district court’s and the parties’ agreed upon claim construction, regardless of whether the construction to which the parties agree is actually the proper construction of that term, citing the Supreme Court’s decision in SAS Institute v. Iancu, 138 S. Ct. 1348 (2018), and the CAFC’s decisions in Koninklijke Philips N.V. v. Google LLC, 948 F.3d 1330 (Fed. Cir. 2020), and In re Magnum Oil Tools International, Ltd., 829 F.3d 1364 (Fed. Cir. 2016).
The Court rejected VLSI’s interpretation of the precedent set by the cases. Instead, they noted that each of these cases in fact stands for the proposition that the petition defines the scope of the IPR proceeding and that the Board must base its decision on arguments that were advanced by a party and to which the opposing party was given a chance to respond. They affirmatively stated that none of the relied upon cases prohibits the Board from construing claims in accordance with its own analysis and may adopt its own claim construction of a disputed claim term. Specifically, as to the case at hand, they noted the parties’ very different understandings of the meaning of the term “die attach,” and that it was clear in the Board proceedings that there was no real agreement on the proper claim construction. They conclude that in such a situation, it was proper for the Board to adopt its own construction of a disputed claim term.
Based thereon, the Court affirmed the claim construction of “force region” and the PTAB’s application of the Oda prior art reference.
Claim 20
Regarding claim 20, VLSI argued that the Board erred in construing the phrase “used for electrical interconnection not directly connected to the bond pad,”. As noted above, the Board had held that this phrase encompasses interconnect layers that are “electrically connected to each other but not electrically connected to the bond pad” or to any other active circuitry. VLSI asserted that under its proposed construction, the Kanaoka reference does not disclose the “used for electrical interconnection” limitation of claim 20, because the metallic layers are connected by the vias only to one another; they do not carry electricity and are not electrically connected to any other components.
The Court agreed with VLSI that the Board’s construction of the phrase “used for electrical interconnection not directly connected to the bond pad” was too broad, noting that two aspects of the claim make this point clear. First, the use of the words “being used for” in the claim imply that some sort of actual use of the metal interconnect layers to carry electricity is required. Second, the recitation of “dummy metal lines” elsewhere in claim 20 implies that the claimed “metal-containing interconnect layers” are capable of carrying electricity; otherwise, there would be no distinction between the dummy metal lines and the rest of the interconnect layer. The Court further noted that the file history of the ’552 patent and amendments made during prosecution provided additional support for this conclusion.
Furthermore, they noted that the phrase “as a result of being used for electrical interconnection not directly to the bond pad” was meant to serve some purpose and should be construed to have some independent meaning, citing Merck & Co. v. Teva Pharms. USA, Inc., 395 F.3d 1364, 1372 (Fed. Cir. 2005) (“A claim construction that gives meaning to all the terms of the claim is preferred over one that does not do so.”). Thus, they concluded that the words “being used for” imply that the interconnect layers are at least capable of carrying electricity.
The Court therefore remanded the patentability determination of claim 20 to the Board to assess Intel‘s obviousness arguments in light of their new construction of the “used for electrical interconnection” limitation.
Take away
The PTAB is not hamstrung by prior claim construction reached in a District Court action. The Board may construe claims in accordance with its own analysis and may adopt its own claim construction of a disputed claim term.
The recitation of an operational function (“being used for”) in a claim should not be ignored in claim construction. The claim language should be taken as a whole and other aspects of the claim (“dummy metal lines”) which infer an interpretation should be considered.
